WORKSHOP PROGRAM

5th International Workshop on
Software and Compilers for Embedded Systems

SCOPES 2001

March, 20 - 22, 2001

Schloss Rheinfels, St. Goar, Germany

TUESDAY, March 20th


14:00 - 14:30
 Introduction (P. Marwedel)
14:30 - 15:30
 Keynote: "Design Automation Technology Challenges for Application-Specific Architecture Platforms"
Pierre Paulin
Director, SoC Platform Automation,
Central R&D
STMicroelectronics

This talk adresses the emerging architectural platform approach to improve time-to-market, and the design automation technologies needed to support it. Architectural platforms can be defined as a domain- or application-specific base design which is easily configured to the specific needs of a given market. Platforms for consumer applications (set-top box, DVD) and network processing will be presented to illustrate the concept. We then focus on key programmable platform components and the embedded software and architecture exploration tools needed to best exploit them.

Coffee break
16:00 - 17:30

SESSION 1: C Compilers for Embedded Processors

Session Chair: Ahmed Jerraya

"A Customizable Compiler Framework for Embedded Systems" (F) (paper)

A. Halambi, A. Shrivastava, N. Dutt, A. Nicolau
University of California, Irvine, CA

"C Compiler Design for an Industrial Network Processor" (F) (paper, slides)

J. Wagner, R. Leupers
University of Dortmund, Germany

"Using the IMPACT VLIW Compiler Framework to Implement a Compiler for a Fixed Point DSP" (F) (paper, slides)

S. Rajagopalan, S. Malik, Princeton University, USA
S. Rajan, Fujitsu Labs of America, USA
G. Araujo, S. Rigo, Instituto de Computacao,Campinas, Brazil

Social Event: Guided tour through the castle

Dinner

WEDNESDAY, March 21st


9:00 - 10:30

SESSION 2: ASIP Design and Code Generation

Session Chair: Jürgen Teich

"Application-Driven Customization for Embedded Processors: The Partitioned Cache Architecture" (F)

P. Petrov, A. Orailoglu
University of California at San Diego, USA

"Using an Energy Aware Compiler Framework to Evaluate Changes in Register File Size towards ASIP-Design" (F) (paper, slides)

L. Wehmeyer, S. Steinke, P. Marwedel
University of Dortmund, Germany
M. K. Jain, M. Balakrishnan
Indian Institute of Technology, Delhi, India

"Tightly Coupled Operation Assignment and Scheduling for VLIW Processors with FACTS" (S)

M. Bekooij, B. Mesman, J. van Meerbergen, J. Jess
Philips Research Labs, The Netherlands

"Compiler Generation in PEAS-III: an ASIP Development System" (S) (paper, slides)

S. Kobayashi, Y. Takeuchi, A. Kitajima, M. Imai
Osaka University, Japan

Coffee break
11:00 - 12:30

SESSION 3: Automatic Tool and Software Generation

Session Chair: Guido Araujo

"Modeling and Simulation Issues of Programmable Architectures" (F) (paper, slides)

A. Hoffmann, A. Nohl, G. Braun, O. Wahlen, H. Meyr
Aachen University of Technology, Germany

"Automatic Targeting of Embedded Systems Software with Application Specific Operating Systems Generation" (F) (paper, slides)

L. Gauthier, S. Yoo, A. Jerraya
TIMA laboratory, Grenoble, France

"Automatic Test Bench Generation for Equivalence Checking of C Programs Based on ATPG techniques" (F) (paper, slides)

M. Fujita, University of Tokyo, Japan
I. Ghosh, Fujitsu Labs of America, USA
12:30 - 14:00

Lunch
14:00 - 15:00 

DISCUSSION

Moderator: Jochen Jess
15:00 - 15:30
 POSTER SESSION
Session Chair: Rainer Leupers

"Co-Design of Custom VLIW-DSP Type Data-path Architecture and its Parallel Program for Loops based on Formal Verification Technique"

K. Seto, Pacific Design Inc.
T. Kuroha, D. Nakatani, K. Asada, M. Fujita University of Tokyo, Japan

"Towards Automatic Parallelisation for Multi-Processor DSPs" (paper, poster)

B. Franke, M. O'Boyle
University of Edinburgh, Great Britain

"Maximizing for Reducing Register Need in Acyclic Schedules" (poster, paper)

S. Touati
INRIA, France

"Modeling and Simulation of Embedded Processors Using Abstract State Machines" (paper, poster)

D. Fischer, J. Teich, R. Weper
University of Paderborn

"A New System for High-Performance Cycle-Accurate Compiled Simulation" (paper, poster)

R. Amicel, F. Bodin
IRISA, France
15:30 - 16:00

Coffee break
16:00 - 17:30

SESSION 4: Code Generation and Optimization

Session Chair: Nikil Dutt

"Bitwidth Sensitive Code Generation in a Custom Embedded Accelerator Design System" (F) (paper)

S. Mahlke, R. Ravindran, M. Schlansker, R. Schreiber, T. Sherwood
HP Labs, Palo Alto, USA

"Integrated Scheduling and Register Allocation - A Resource Based Approach" (F) (paper)

T. Zeitlhofer, B. Wess
Vienna University of Technology, Austria

"Retargetable Code Optimisation by Integer Linear Programming" (S) (paper, slides)

D. Kästner
Saarland University, Germany

"Evolutionary Code Generation for Architectures with Multiple Data-Memory Banks" (S) (paper, slides)

S. Fröhlich, B. Wess
Vienna University of Technology, Austria

Social Event: boat trip on the river Rhine including dinner buffet

evening event sponsored by         

THURSDAY, March 22nd


9:00 - 10:30

SESSION 5: Embedded Software Design

Session Chair: Scott Mahlke

"Software-controlled Processor Speed Setting for Low-Power Streaming Multimedia" (F) (paper, slides)

A. Acquaviva, L. Benini, B. Riccó
Universitá di Bologna, Italy

"A New Codesign Methodology for Embedded Multiprocessor-Based Systems and Systems-on-Chip that Exploits Efficient Code Generation" (F) (paper, slides)

R. Janka, Cadence Design Systems, Atlanta, USA
L. Wills, Georgia Institute of Technology, Atlanta, USA

"Space-time memory access patterns : a step towards the object-oriented design of low-cost distributed platforms" (S)

T. Omnès, F. Catthoor IMEC, Leuven, Belgium

"Whole Program Compilation for Embedded Software: the ADSL Experiment" (S) (paper, slides)

J. Cockx
IMEC Leuven, Belgium

Coffee break
11:00 - 11:45

SESSION 6: Program Analysis and Optimization

Session Chair: Yoshinori Takeuchi

"Data Locality Analysis and Optimization" (F) (paper, slides)

H. Lin, W. Wolfe
Princeton University, USA

"Value Range Analysis with Modulo Interval Arithmetic" (S) (paper, slides)

T. Nakanishi, A. Fukuda
Nara Institute of Science and Technology, Japan
11:45 - 12:45
 DISCUSSION
Moderator: Peter Marwedel
12:45
 Lunch

(F) Full paper - 30 min presentation

(S) Short paper - 15 min presentation